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Memory Slave Controller IP forms a bridge between the SD host and user interface, enabling the data transfer between each other. This IP will send the response to the SD host depending on the command issued and also communicates with the user through a register interface for control and status. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI4 -lite or AHB complaint interface for accessing through processor and other is simple general-purpose interface which can be used without the processor.
SD memory slave IP is tested in Zynq 7000 based devices from AMD/Xilinx using ZED Board and PMOD SD to interface with SD host using SD male to male custom cable. The baremetal version with DDR connected to FPGA targeted as memory variant of the IP is tested in this setup.
SD memory slave IP is tested in ProASIC3 based devices from Microchip using iWave’s ProASIC3 custom dev kit which has the built in SD connector to interface with SD host. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.
SD memory slave IP is tested in SmartFusion 2 based devices from Microchip using SmartFusion2 Advanced Development Kit (M2S150-ADV-DEV-KIT) and iWave FMC daughter card with SD to interface with SD host using SD male to male custom cable. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.
SD memory slave IP is tested in Crosslink NX based devices from Lattice using Crosslink NX dev kit and PMOD SD to interface with SD host using SD male to male custom cable. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.
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