Specification

• • Hardware features
    • Transmit buffer (2 Byte Depth)
    • Receive buffer (4 Byte Depth)
    • Interrupt control function
    • DMA request: 2 for TX and 2 for Rx
    • Overrun error detection
    • Baud rate generator
    • Self-loop back test function
    • DPLL supported
  • Communication protocol features
    • Start-stop synchronization
      • Character bit length: 5, 6, 7, 8
      • Stop bit length: 1, 1.5, 2
      • Clock rate: x1, x16, x32, x64
      • Parity generation, check
      • Framing error detection
      • Break generation, detection
    • Character oriented protocol (COP)
      • Operating mode: Mono-sync, Bi-sync, External sync
      • Character bit length: 5, 6, 7, 8
      • SYNC character bit length: 6, 8
      • Character synchronization: internal/external
      • Block check sequence (BCS) generation, check: CRC16, CRC-CCITT
      • Parity generation, check
      • SYNC character automatic transmission, detection, rejection
    • Bit oriented protocol (BOP) – HDLC, SDLC, SDLC Loop
      • Operation mode: HDLC (High-level Data Link Control), SDLC
      • (Synchronous Data Link Control), SDLC Loop
      • Flag transmission, detection
      • Zerinsertion, rejection
      • Address field detection (1 byte)
      • FCS (Frame Check Sequence) generation, detection
      • Short frame detection
      • Abort automatic transmission, detection
      • Idle detection
      • GAhead detection
      • Transmit number data control
  • Processing data format
    • Encode/decode of NRZ (Non-Return to Zero)
    • Encode/decode of NRZI (Non-Return to Zero Inverted)
    • Encode/decode of FM (Frequency Modulation)
    • Decode in Manchester mode