New Release: NAND Flash Controller IP Core Updated with BCH Code for ECC Algorithm

iWave Systems is pleased to inform you that ECC algorithm supported by the NAND Host controller IP is updated to BCH code.

Product: NAND Host Controller IP Core
Feature Updated: ECC algorithm supported by the NAND Host controller is updated to BCH code which can correct the errors up to 8 bits per 512 bytes

Details: –

ECC (Error Correction Code) logic is essential for NAND flash devices due to the inherent nature of generating bit errors. To enhance the overall reliability of flash devices, an efficient ECC algorithm is crucial for correcting errors during program, read, and data retention operations.

Recognizing the increasing demand for error correction in NAND, iWave has upgraded its NAND host controller. This update includes support for the widely recognized BCH code, capable of correcting errors up to 8 bits per 512 bytes of data. This enhancement broadens the applicability of the host controller to accommodate multiple NAND devices requiring up to 8 bits of error correction.

A NAND Flash Controller IP implements the necessary logic required to interface user data with a NAND Flash memory device. The NAND Flash Controller IP Core performs operations such as Block erase, Page program, and read operations with other mandatory commands which enables access for the NAND device to the user. iWave’s ONFI 2.0 compliant NAND Flash Controller IP Core is a fully featured, easy-to-use, synthesizable design that can be easily integrated into any SoC or non-SoC FPGA-based platform. The NAND Flash IP Core also adds a faster, asynchronous, or synchronous I/O interface to meet today’s demanding high-performance needs.

For more information, please get in touch with mktg@iwavesystems.com.