NAND Flash Controller IP: Enabling Efficient Data Interface with Flash Memory Devices.

A NAND Flash Controller IP implements the necessary logic required to interface user data with a NAND Flash memory device. The NAND Flash Controller IP Core performs operations such as Block erase, Page program, and read operations with other mandatory commands which enables access for the NAND device to the user.

iWave’s ONFI 2.0 compliant NAND Flash Controller IP Core is a fully featured, easy-to-use, synthesizable design that can be easily integrated into any SoC or non-SoC FPGA-based platform. Designed to support SLC flash memories, the NAND Flash Controller is flexible to use and implement. The NAND Flash IP Core also adds a faster, asynchronous, or synchronous I/O interface to meet today’s demanding high-performance needs.

The iWave NAND flash IP core allows a designer to quickly and efficiently integrate NAND flash memory functionality into their designs to make use of NAND flash memory capabilities to their design without having to develop the controller logic from scratch. By using an IP core, customers can reduce development time, cost, and risk, and focus on adding value to their end products.

The Key features supported by iWave’s NAND host controller IP are,

• Compliant with ONFI specification
• 8 or 16 bit Asynchronous and synchronous Interface to NAND device
• Supports SLC NAND Flash Memory
• Page Size: Up to 16K Byte (Compile time configurable)
• Supports all mandatory commands
• Separate Chip Select, Write Enable, Read Enable, and Ready/Busy for each die and the IO signals are shared between the die
• Hamming code or BCH code for ECC logic which can correct up to 8-bit errors per 512 bytes
• Supports software ECC or ECC by the controller or on-die ECC
• 16K-Byte Buffer for writing and reading data
• AXI4-lite interfaces towards the processor for register access
• AXI4-MM interface towards the processor for data transfer

The NAND Flash Controller IP has been validated on multiple FPGA platforms including Xilinx, Intel, Lattice, and Microchip. Check out the resource utilization document for more information. iWave’s NAND host controller IP has been thoroughly validated with multiple FPGA device families and is well suited for various defense, space, and avionics applications.
NAND Flash Controller IP is available in three variants depending on the availability of the processor on the FPGA device selected by the user.

• File system using the ARM core of the SOC devices

• • The NAND Linux driver implemented in the ARM core interfaces with the NAND host controller using the AXI4 lite interface for register access and AXI4 memory mapped interface for data transfer.
  • NAND host controller implemented in the FPGA communicates with the NAND devices using the NAND protocol defined as per the ONFI specification.
  • Supports the well-known industry standard flash file systems like JFFS2 and UBI