Documents

BUY NOW

Documents

BUY NOW
UDP IP Core

UDP/IP Core

UDP/IP Core

The UDP/IP Hardware protocol stack offloads UDP encapsulation task from the host processor enabling media streaming with speed up to 40G even in a processor less non-SoC designs, making it ideal for any standalone operation. This IP core provides an effective infrastructure to implement high-speed communication between the FPGA and other network devices. It supports easy to use AXI streams on the FPGA to connect to the network devices.

Categories: ,

SPECIFICATION

  • Easy integration with 1G, 10G, and 40G Ethernet MAC
  • Configurable number of UDP Transmit & Receive channels from 1 to 32
  • IPV4 support without packet fragmentation
  • Supports GMII/RGMII/SGMII/XGMII/XLGRMII interfaces
  • Echo-Request & Reply messages (“ping”) of the Internet Control Message Protocol (ICMP) used to test network connectivity
  • Address Resolution Protocol (ARP) for proper functioning over the internet
  • UDP & IP checksum generation and validation support
  • 32bit, 64bit, and 128bit AXI stream interface for transmission & reception of user data and 32bit AXI4-Lite interface for handling control and status registers
  • Configurable buffer sizes for easy SoC integration
  • Supports optional Dynamic Host Configuration Protocol (DHCP) client

HIGHLIGHTS

  • Bring full UDP/IP connectivity to FPGAs even if no CPU is available
  • Offload UDP/IP processing into programmable logic
  • Enable media streaming with speed up to 40G
  • Offers a configurable number of UDP transmit and receive channels.

RELATED VIDEOS

Webinar: Enabling Storage, Space and Avionics: iWave IP Cores & ODM Expertise on Microchip FPGAs

NAND Host Controller IP Core: An Overview

Demonstration of eMMC 5.1 Host Controller IP Core

Related products

img

SATA 3.0 Bridge Controller

Aligns with SATA 3.0 specification, providing bridging features between SATA Host & Device

Learn More
img

VME Slave IP Core (VME to AXI Bridge)

Aligns with ANSI/VITA1.0-1994 standard, implementing VME data transfer in slave configuration

Learn More
img

PCI Controller

Facilitates efficient transition to future processors by bridging the PCI bus and user interface

Learn More
img

PCIe to SD/MMC Bridge

Converts the PCIe to SD bus interface or MMC bus interface realized by SD/MMC protocol

Learn More

Copyright © 2022 iWave Systems Technologies Pvt. Ltd.

Linkedin-in Youtube Facebook-f