Zynq UltraScale+ MPSoC ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 SOM

Zynq UltraScale+ MPSoC ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 SOM

iW-RainboW-G36M®

  • AMD Xilinx’s ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 Compatible Zynq Ultrascale+ MPSoC SoM
  • 64bit, 4GB PS DDR4 RAM (Upgradable)
  • 16 bit, 2GB PL DDR4 RAM (Upgradable)
  • 4 High-Speed Transceiver lanes (Up to 12.5Gb/s)
  • 16GB eMMC Flash (Upgradable)
  • On-SOM Gigabit Ethernet PHY & USB2.0 transceiver
  • RGMII Interface or ULPI Interface x 1

On Board Features:

ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 – Zynq Ultrascale+ MPSoC (SFVC784)

Processing System (PS/Processor)

  • Quad-core Arm Cortex-A53 MPCore @1.5GHz, Dual-core Arm Cortex-R5 MPCore @600MHz
  • Arm Mali-400MP2 GPU @677MHz

Programming Logic (PL/FPGA)

  • Up to 256.2K Logic cells & 117.12K LUTs
  • High Speed GTH Transceiver Lanes x 4 (Up to 12.5Gb/s)

 

RAM Memory

Processing System (PS):

  • 64bit, 4GB DDR4 RAM with ECC

Programmable Logic (PL/FPGA):

  • 16bit, 2GB DDR4 RAM

 

On Board Flash
  • 256MB QSPI Flash for boot & storage (Optional)
  • 16GB eMMC Flash for boot & storage (Expandable up to 128GB)
  • EEPROM (4Kbit)

 

240pin High-Speed High-Density Board to Board Connector 1 Interfaces:

  • PS GTR Transceiver Lanes x 4 (Up to 6.0Gb/s)
  • HP Bank IOs – Up to 481 LVDS/96 Single Ended (SE)
  • HD Bank IOs – Up to 24 LVDS / 48SE
  • ADC Input pins – Up to 32 Differential/Single Ended from HP Banks
  • ADC Input pins – Up to 16 Differential/Single Ended from HD Banks
  • System Synchronization Differential Clock Output/Input

240pin High-Speed High-Density Board to Board Connector 2 Interfaces:

From PS Block
  • GEM3 RGMII Interface or ULPI Interface x 1
  • Gigabit Ethernet x 1 Port (through On SOM Gigabit Ethernet PHY)
  • USB2.0 OTG x 1 Port (through On-SOM USB2.0 transceiver)
  • SD (4bit) x 1
  • Debug UART & Data UART x 1
  • I2C x 2 Port
  • CAN Interface x 22
  • JTAG x 1

 

From PL Block
  • High Speed GTH Transceiver Lanes x 4 (Up to 12.5Gbps)
  • HD Bank IOs – 17 LVDS/36 Single Ended
  • GC Inputs – 6 Differential/Single Ended
  • ADC Input Pins – Up to 17 Differential/Single Ended from HD Banks
  • SPI with (2CS) x 1
  • 1PPS In/Out

Other On-Board Features

  • Trusted Platform Module 2.0 (TPM)
  • Fan Header
  • USB 2.0 PHY
  • Gigabit Ethernet PHY
  • 10-Bit Clock Synthesizer

OS Support

  • Linux BSP – Petalinux/vivado 2023.1
  • Baremetal BSP – Vivado 2023.1

General Features:

Power Input

+5VDC +/- 5% Input from Board-to-Board Connector 2

Form Factor

50mm X 60mm (REN)

Operating Temperature

-40°C to +85°C (Industrial)

Environment Specification

RoHS & REACH Compliant

Compliance

CE*

Notes:
*Under Progress
1 2 PL IOs can be used as PL PCIe reset functionality or PL DIFF/SE in Board-to-board connector.
2 CAN0 is available when feedback clock functionality in QSPI Flash is not using.

DEVELOPMENT KIT

  • FMC+ High Serial Pin Count (HSPC) Connector
  • Debug UART and JTAG through USB Type-C
  • Dual 1GBE Ethernet through RJ45
  • USB2.0 OTG interface through USB Type-C Connector
  • PCIe x1/x2/x4 Gen2 Connector
  • USB 3.0 Connector
  • DP  & M.2 SATA Connector
  • Micro SD & PMOD Connector
  • RTC Coin Cell Holder
  • Header for UART, CAN, SPI and GPIOs
  • Form Factor: 120mm x 120mm

Custom Design Sevices

iWave provides end-to-end ODM services, from concept to production, leveraging our in-house expertise in hardware design, software development, FPGA design, and mechanical enclosure design. The FPGA expertise at iWave includes RTL, high speed bus interface and transceivers, storage, video, networking, and high-speed ADC/DAC with the entire product lifecycle, from initial concept to mass production and ongoing support.

THERMAL SOLUTIONS

For any highly integrated System on Modules, thermal design is a very important factor. iWave supports a Fan sink for MPSoC Based SOM.

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